/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */


`include "defines.v"

module id_ex(
	input wire	clk,
	input wire	rst,
	input wire[`StallBus] stall,

	input wire [`RegBus]	id_inst,

	// source from inst decode stage
	input wire [`AluOpBus]	id_aluop,
	input wire [`AluSelBus] id_alusel,
	input wire [`RegBus]	id_reg1,
	input wire [`RegBus]	id_reg2,
	input wire [`RegBus]	branch_target_op1_i,
	input wire [`RegBus]	branch_target_op2_i,
	input wire [`RegAddrBus] id_wd,
	input wire		id_wreg,
	input wire		flush_inst_i,

	// branch
	input wire[`RegBus]	id_link_address,

	output reg[`RegBus]	ex_inst,
	// sink to execute info
	output reg[`AluOpBus]	ex_aluop,
	output reg[`AluSelBus]	ex_alusel,
	output reg[`RegBus]	ex_reg1,
	output reg[`RegBus]	ex_reg2,
	output reg[`RegBus]	branch_target_op1_o,
	output reg[`RegBus]	branch_target_op2_o,
	output reg[`RegAddrBus]	ex_wd,
	output reg		ex_wreg,

	// branch
	output reg[`RegBus]	ex_link_address
);


	always @ (posedge clk) begin
		if (rst == `RstEnable) begin
			ex_aluop	<= `EXE_NOP_OP;
			ex_alusel	<= `EXE_RES_NOP;
			ex_reg1		<= `ZeroWord;
			ex_reg2		<= `ZeroWord;
			ex_inst		<= `NOP_INST;
			ex_wd		<= `NOPRegAddr;
			ex_wreg		<= `WriteDisable;
			ex_link_address <= `ZeroWord;
			branch_target_op1_o <= `ZeroWord;
			branch_target_op2_o <= `ZeroWord;
		end else if (flush_inst_i == 1'b1) begin
			ex_aluop	<= `EXE_NOP_OP;
			ex_alusel	<= `EXE_RES_NOP;
			ex_reg1		<= `ZeroWord;
			ex_reg2		<= `ZeroWord;
			ex_inst		<= `NOP_INST;
			ex_wd		<= `NOPRegAddr;
			ex_wreg		<= `WriteDisable;
			ex_link_address <= `ZeroWord;
			branch_target_op1_o <= `ZeroWord;
			branch_target_op2_o <= `ZeroWord;
		end else if (stall[2] == `Stop && stall[3] == `NoStop) begin
			ex_aluop	<= `EXE_NOP_OP;
			ex_alusel	<= `EXE_RES_NOP;
			ex_reg1		<= `ZeroWord;
			ex_reg2		<= `ZeroWord;
			ex_inst		<= `NOP_INST;
			ex_wd		<= `NOPRegAddr;
			ex_wreg		<= `WriteDisable;
			ex_link_address <= `ZeroWord;
			branch_target_op1_o <= `ZeroWord;
			branch_target_op2_o <= `ZeroWord;
		end else if (stall[2] == `NoStop) begin
			ex_aluop	<= id_aluop;
			ex_alusel	<= id_alusel;
			ex_reg1		<= id_reg1;
			ex_reg2		<= id_reg2;
			ex_inst		<= id_inst;
			ex_wd		<= id_wd;
			ex_wreg		<= id_wreg;
			ex_link_address <= id_link_address;
			branch_target_op1_o <= branch_target_op1_i;
			branch_target_op2_o <= branch_target_op2_i;
		end
	end

endmodule
